SN74ALVC3631_07 Datasheet, PDF (18/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
CLKA
tsk(1)†
1
IR FIFO Filled to First Retransmit Word
2
tpd(C-IR)
One or More Write Locations Available
CLKB
RTM
ÌÌÌÌÌÌÌÌ ^tsu(EN) ÏÏ^tÏÏ^h(ENÏÏ⁾ ÏÏ
† _{tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time}
between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown.
Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available
CLKA
tsk(2)‡
1
AF (D§ – Y) or More Words Past First Retransmit Word
2
tpd(C-AE)
(Y + 1) or More Write Locations Available
CLKB
RTM
ÌÌÌÌÌÌÌÌ ^tsu(EN) ÏÏÏÏ^th(ÏÏ^EN)ÏÏÏÏ
‡ _{tsk(2) is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time}
between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown.
§ _{D = 512 for the SN74ALVC3631; D = 1024 for the SN74ALVC3641; D = 2048 for the SN74ALVC3651.}
NOTE A: Y is the value loaded in the AF flag offset register.
Figure 13. AF Timing From the End of Retransmit Mode
When (Y + 1) or More Write Locations Are Available
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