SN74ALVC3631_07 Datasheet, PDF (23/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 30 pF (see Figures 1 through 16)
PARAMETER
’ALVC3631-10 ’ALVC3631-15 ’ALVC3631-20
’ALVC3641-10 ’ALVC3641-15 ’ALVC3641-20
’ALVC3651-10 ’ALVC3651-15 ’ALVC3651-20
UNIT
MIN MAX MIN MAX MIN MAX
fmax
ta
tpd(C-IR)
tpd(C-OR)
tpd(C-AE)
tpd(C-AF)
tpd(C-MF)
Access time, CLKB↑ to B0–B35
Propagation delay time, CLKA↑ to IR
Propagation delay time, CLKB↑ to OR
Propagation delay time, CLKB↑ to AE
Propagation delay time, CLKA↑ to AF
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high
and CLKB↑ to MBF2 low or MBF1 high
100
66.7
2 7.5
2 9.5
1 6.5
1
8
1 6.5
1
8
1
8
1
8
1
8
1
8
0 6.5
0
8
50
MHz
2 11.5 ns
1
10 ns
1
10 ns
1
10 ns
1
10 ns
0
10 ns
tpd(C-MR)
Propagation delay time,
CLKA↑ to B0–B35† and CLKB↑ to A0–A35‡
2
11
2
12
2
13 ns
tpd(M-DV)
tpd(R-F)
ten
Propagation delay time, MBB to B0–B35 valid
Propagation delay time, RST low to AE low and AF high
Enable time, CSA and W/RA low to A0–A35 active and CSB
low and W/RB high to B0–B35 active
2
9
1 6.5
2
10
2
10
1 7.5
2
11
2
12 ns
1 8.5 ns
2
12 ns
Disable time, CSA or W/RA high to A0–A35 at high
tdis
impedance and CSB high or W/RB low to B0–B35 at high
impedance
1
10
† _{Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high}
‡ _{Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high}
1
11
1
12 ns
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