SN74ALVC3631_07 Datasheet, PDF (15/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

tc
tw(CLKH)
CLKB
tw(CLKL)
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
CSB Low
W/RB _High
MBB
ENB
OR
B0–B35
Low
ÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌ ^tsu(EN)
th(EN)
High
ta
FIFO Output Register
Next Word From FIFO
CLKA
IR
tsk(1)†
tw(CLKH)
1
FIFO Full
tc
tpd(C-IR)
tw(CLKL)
2
tpd(C-IR)
CSA Low
W/RA
MBA
ENA
A0–A35
ÌÌÎÎÏÏ^HiÌÌÎÎÏÏ^gh ÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏÌÌÎÎÏÏ^ttssÌÌÎÎÏÏ_tuus((uEE(ÌÌÎÎÏÏ_DNN))) ÌÌÎÎ_WrÎÎÌÌ_{ite ÏÏÎÎÌÌ}^ttthhh(((_{ÏÏÎÎÌÌ}^EEDNN)))_{ÏÏÎÎÌÌÏÏÎÎÌÌÏÏÎÎÌÌÏÏÎÎÌÌÏÏÎÎÌÌÏÏÎÎÌÌ}
† _{tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time}
between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown.
Figure 7. IR-Flag Timing and First Available Write When FIFO Is Full
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