SN74ALVC3631_07 Datasheet, PDF (22/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
’ALVC3631-10 ’ALVC3631-15 ’ALVC3631-20
’ALVC3641-10 ’ALVC3641-15 ’ALVC3641-20
’ALVC3651-10 ’ALVC3651-15 ’ALVC3651-20
UNIT
MIN MAX MIN MAX MIN MAX
fclock
tc
tw(CH)
tw(CL)
tsu(D)
Clock frequency, CLKA or CLKB
Clock cycle time, CLKA or CLKB
Pulse duration, CLKA and CLKB high
Pulse duration, CLKA and CLKB low
Setup time,
A0–A35 before CLKA↑ and B0–B35 before CLKB↑
100
10
4
4
66.7
15
6
6
50 MHz
20
ns
8
ns
8
ns
2.5
3.5
4.5
ns
tsu(EN)
Setup time, CSA, W/RA, ENA, and MBA before CLKA↑;
CSB, W/RB, ENB, MBB, RTM, and RFM before CLKB↑
3.5
5
6
ns
tsu(RS)
Setup time, RST low before CLKA↑ or CLKB↑^†
6
7
8
ns
tsu(FS)
tsu(SD)‡
tsu(SEN)‡
Setup time, FS0 and FS1 before RST high
Setup time, FS0/SD before CLKA↑
Setup time, FS1/SEN before CLKA↑
12
13
14
ns
3.5
5
6
ns
3.5
5
6
ns
th(D)
Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑
0.5
0.5
0.5
ns
th(EN)
Hold time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, RFM, and MBB after CLKB↑
0.5
0.5
0.5
ns
th(RS)
Hold time, RST low after CLKA↑ or CLKB↑^†
3.5
5
6
ns
th(FS)
Hold time, FS0 and FS1 after RST high
0.5
0.5
0.5
ns
th(SP)‡
Hold time, FS1/SEN high after RST high
0.5
0.5
0.5
ns
th(SD)‡
Hold time, FS0/SD after CLKA↑
0.5
0.5
0.5
ns
th(SEN)‡ Hold time, FS1/SEN after CLKA↑
0
0
0
ns
tsk(1)§
Skew time between CLKA↑ and CLKB↑ for OR and IR
7
9
11
ns
tsk(2)§
Skew time between CLKA↑ and CLKB↑ for AE and AF
8
12
16
ns
† _{Requirement to count the clock edge as one of at least four needed to reset a FIFO}
‡ _{Applies only when serial load method is used to program flag offset registers}
§ _{Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and}
CLKB cycle.
22
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265