SN74ALVC3631_07 Datasheet, PDF (14/29 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
CLKA
tc
tw(CLKH)
tw(CLKL)
CSA Low
W/RA High
tsu(EN)
MBA
ÎÎÎÎÎÎÎÎÎÎÎÎÎ _ENA
tsu(EN)
ÌÌÎÌÌÎ^tthh((EEÌÌÎ^NN)) ÌÌÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IR High
ÏÏÏÏÏ ^A0–A35
tsu(D)
W1
ÏÏ^th(DÏ⁾ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
tsk(1)†
tw(CLKH)
tc
tw(CLKL)
CLKB
OR
1
Old Data in FIFO Output Register
2
3
tpd(C-OR)
tpd(C-OR)
CSB Low
W/RB High
MBB Low
EN^ÎÎB ^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}_t^ÎÎ_atsu^{ÎÎ(ENÎÎ) ÌÌtÌÌh(ENÌÌ) ÌÌÌÌÌÌÌÌÌÌ}
B0–B35
Old Data in FIFO Output Register
W1
† _{tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the FIFO}
output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1), then the transition of
OR high and the first word load to the output register can occur one CLKB cycle later than shown.
Figure 6. OR-Flag Timing and First-Data-Word Fall Through When FIFO Is Empty
14
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