DS125BR800 Datasheet, PDF (5/59 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel Repeater With Input Equalization and Output De-Emphasis

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DS125BR800
SNLS426E – AUGUST 2012 – REVISED JANUARY 2015
Pin Functions⁽¹⁾ (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
MODE
21
I, 4-LEVEL,
MODE control pin selects operating modes.
LVCMOS
Tie 1 kΩ to GND = PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6
Gbps)
FLOAT = AUTO Rate Select (for PCIe)
Tie 20 kΩ to GND = PCIe Gen-3 without De-emphasis
Tie 1 kΩ to VDD = PCIe Gen-3 with De-emphasis
See Table 6
SD_TH
26
I, 4-LEVEL,
Controls the internal Signal Detect Threshold.
LVCMOS
For datarates above 8 Gbps the Signal Detect function should be
disabled to avoid potential for intermittent data loss. See Table 5 for
additional information.
CONTROL PINS — BOTH PIN AND SMBus MODES (LVCMOS)
RXDET
22
I, 4-LEVEL,
The RXDET pin controls the receiver detect function. Depending on the
LVCMOS
input level, a 50 Ω or >50 kΩ termination to the power rail is enabled.
See Table 4.
RESERVED
23
I, FLOAT
Float (leave pin open) = Normal Operation
VDD_SEL
25
I, LVCMOS
Controls the internal regulator
FLOAT = 2.5-V mode
Tie GND = 3.3-V mode
PWDN
52
I, LVCMOS
Tie High = Low power - power down
Tie GND = Normal Operation
See Table 4.
OUTPUTS
ALL_DONE
27
O, LVCMOS
Valid Register Load Status Output
HIGH = External EEPROM load failed
LOW = External EEPROM load passed
POWER
VIN
24
Power
In 3.3-V mode, feed 3.3 V to VIN
In 2.5-V mode, leave floating
VDD
9, 14, 36, 41, 51 Power
Power supply pins CML/analog
2.5-V Mode, connect to 2.5-V supply
3.3-V mode, connect 0.1-µF cap to each VDD pin
See Power Supply Recommendations for proper power supply
decoupling.
GND
DAP
Power
Ground pad (DAP - die attach pad)
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