DS125BR800 Datasheet, PDF (14/59 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel Repeater With Input Equalization and Output De-Emphasis

DS125BR800
SNLS426E – AUGUST 2012 – REVISED JANUARY 2015
www.ti.com
Level
8
9
10
11
12
13
14
15
16
DEMA1
DEMB1
R
Float
Float
Float
Float
1
1
1
1
Table 3. Output Voltage and De-Emphasis Settings (continued)
DEMA0
DEMB0
1
0
R
Float
1
0
R
Float
1
VOD Vp-p
1.1
1.1
1.2
1.2
1.2
1.3
1.3
1.3
1.3
DEM dB⁽¹⁾
- 3.5
-6
0
- 3.5
-6
0
- 3.5
-6
-9
Inner Amplitude
Vp-p
0.7
0.6
1.2
0.8
0.6
1.3
0.9
0.7
0.5
Suggested Use⁽²⁾
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 < 5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 < 5 inch 4–mil trace
FR4 10 inch 4–mil trace
FR4 15 inch 4–mil trace
FR4 20 inch 4–mil trace
PWDN
(PIN 52)
0
0
0
0
1
RXDET
(PIN 22)
0
Tie 20 kΩ
to GND
Float
(Default)
1
X
SMBus REG
bit [3:2]
00
01
10
11
Table 4. RX-Detect Settings
Input Termination
Hi-Z
Pre Detect: Hi-Z
Post Detect: 50 Ω
Pre Detect: Hi-Z
Post Detect: 50 Ω
50 Ω
High Impedance
Recommeded
Use
Comments
X
Manual RX-Detect, input is high impedance mode
PCIe Only
Auto RX-Detect, outputs test every 12 msec for 600
msec then stops; termination is Hi-Z until detection;
once detected input termination is 50 Ω.
Reset function by pulsing PWDN high for 5 µsec then
low again
PCIe Only
Auto RX-Detect, outputs test every 12 msec until
detection occurs; termination is Hi-Z until RX detection;
once detected input termination is 50 Ω.
All Others Manual RX-Detect, input is 50 Ω.
X
Power down mode, input is Hi-Z, output drivers are
disabled.
Used to reset RX-Detect State Machine when held high
for 5 µsec.
8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
Unlike PCIe systems, SAS/SATA (up to 6 Gbps) systems use a low speed Out-Of-Band or OOB communications
sequence to detect and communicate between Controllers/Expanders and target drives. This communication
eliminates the need to detect for endpoints like PCIe. For SAS/SATA systems, it is recommended to tie the
RXDET pin high. This will ensure any OOB sequences sent from the Controller/Expander will reach the target
drive without any additional latency due to the termination detection sequence defined by PCIe.
Table 5. Signal Detect Threshold Level⁽¹⁾
SD_TH
(PIN 26)
0
R
F (default)
1
SMBus REG Bit
[3:2] and [1:0]
10
01
00
11
Assert Level (typ)
210 mVp-p
160 mVp-p
180 mVp-p
190 mVp-p
De-assert Level (typ)
150 mVp-p
100 mVp-p
110 mVp-p
130 mVp-p
(1) VDD = 2.5 V, 25°C and 0101 pattern at 8 Gbps
8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
Signal detect bandwidth limitations combined with high levels of signal attenuation can result in intermittent data
loss above 8 Gbps. This data loss can be eliminated by disabling automatic detection and forcing the Signal
Detect function to be always "on". This programming requires SMBus control over the DS125BR800 to be
present. The Signal Detect function is controlled for each channel independently. The register programming
sequence is shown below:
1. Write register 0x06 = 0x18 //* Enable SMBus register programming
14
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS125BR800