DS125BR800 Datasheet, PDF (26/59 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel Repeater With Input Equalization and Output De-Emphasis

DS125BR800
SNLS426E – AUGUST 2012 – REVISED JANUARY 2015
Register Maps (continued)
Address Register Name
Bit
0x08
Override
7
Pin Control
6
5
4
3
2
0x09
0x0A
1
0
Reserved
7:0
Signal Detect Monitor
7:0
0x0B
Reserved
7
6:0
0x0C
Reserved
7:0
0x0D
CH0 - CHB0
7:3
Signal Detect
2
1
0
www.ti.com
Table 10. SMBUS Slave Mode Register Map (continued)
Field
Reserved
Override SD_TH
Reserved
Override IDLE
Override RXDET
Override MODE
Reserved
Reserved
Reserved
SD_TH Status
Reserved
Reserved
Reserved
Reserved
SD Reset
SD Preset
Reserved
Type
R/W
Default
0x00
R/W 0x00
R
0x00
R/W 0x00
R/W 0x70
R/W 0x00
R/W 0x00
EEPROM Bit
Yes
Yes
Yes
Yes
Yes
Yes
Description
Set bit to 0.
1: Block SD_TH pin control
0: Allow SD_TH pin control
Set bit to 0.
1: IDLE control by registers
0: IDLE control by signal detect
1: Block RXDET pin control
0: Allow RXDET pin control
1: Block MODE pin control
0: Allow MODE pin control
Set bit to 0.
Set bit to 0.
Set bits to 0
CH7 - CH0 Internal Signal Detector Indicator
[7]: CH7 - CHA_3
[6]: CH6 - CHA_2
[5]: CH5 - CHA_1
[4]: CH4 - CHA_0
[3]: CH3 - CHB_3
[2]: CH2 - CHB_2
[1]: CH1 - CHB_1
[0]: CH0 - CHB_0
0 = Signal detected at input (active data)
1 = Signal not detected at input (idle state)
NOTE: These bits only function when RATE pin = FLOAT
Set bits to 0
Set bits to 111 0000'b
Set bits to 0
Set bits to 0.
1: Force signal detect "off"
0: Normal operation
1: Force signal detect "on"
0: Normal operation
Set bit to 0.
26
Submit Documentation Feedback
Product Folder Links: DS125BR800
Copyright © 2012–2015, Texas Instruments Incorporated