DS125BR800 Datasheet, PDF (4/59 Pages) Texas Instruments – Low-Power 12.5-Gbps 8-Channel Repeater With Input Equalization and Output De-Emphasis

DS125BR800
SNLS426E – AUGUST 2012 – REVISED JANUARY 2015
www.ti.com
PIN
NAME
NO.
DIFFERENTIAL HIGH SPEED I/O'S
INB_0+, INB_0-, INB_1+, 1, 2, 3, 4,
INB_1-, INB_2+, INB_2- 5, 6, 7, 8,
,INB_3+, INB_3-,
INA_0+, INA_0-, INA_1+, 10, 11, 12, 13,
INA_1-, INA_2+, INA_2- 15, 16, 17, 18
,INA_3+, INA_3-
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-,
45, 44, 43, 42,
40, 39, 38, 37
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
35, 34, 33, 32,
31, 30, 29, 28
CONTROL PINS — SHARED (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
SDA
49
AD0-AD3
54, 53, 47, 46
READ_EN
26
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19,
46, 47
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50,
53, 54
Pin Functions⁽¹⁾
TYPE
DESCRIPTION
I
Inverting and non-inverting CML differential inputs to the equalizer. On-
chip 50 Ω termination resistor connects INB_n+ to VDD and INB_n- to
VDD when enabled.
AC coupling required on high-speed I/O
I
Inverting and non-inverting CML differential inputs to the equalizer. On-
chip 50 Ω termination resistor connects INA_n+ to VDD and INA_n- to
VDD when enabled.
AC coupling required on high-speed I/O
O
Inverting and non-inverting 50 Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
O
Inverting and non-inverting 50 Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
AC coupling required on high-speed I/O
I, 4-LEVEL,
LVCMOS
System Management Bus (SMBus) Enable pin
Tie 1 kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1 kΩ to GND = Pin Mode
I, 2-LEVEL,
LVCMOS,
O, OPEN Drain
I, 2-LEVEL,
LVCMOS,
O, OPEN Drain
I, 4-LEVEL,
LVCMOS
I, 2-LEVEL,
LVCMOS
Clock output when loading EEPROM configuration, reverting to SMBus
clock input when EEPROM load is complete (ALL_DONE = 0). External
2 kΩ to 5 kΩ pull-up resistor to VDD (2.5-V Mode) or VIN (3.3-V Mode)
recommended as per SMBus interface standards.
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
open drain output. External 2 kΩ to 5 kΩ pull-up resistor to VDD (2.5-V
Mode) or VIN (3.3-V Mode) recommended as per SMBus interface
standards.
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
There are 16 addresses supported by these pins. Pins must be tied LOW
or HIGH when used to define the device SMBus address.
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
The pins are active only when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 2.
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver. The pins are only active when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
DEMA[1:0] pins and bank B is controlled with the DEMB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The DEMA[1:0] pins are converted to SMBUS SCL/SDA
and DEMB[1:0] pins are converted to AD0, AD1 inputs.
See Table 3.
(1) LVCMOS inputs without the FLOAT conditions must be driven to a logic low or high at all times or operation is not guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V Mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
For 2.5-V Mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
4
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