BQ25890H Datasheet, PDF (5/66 Pages) Texas Instruments – I2C Controlled Single Cell 5-A Fast Charger

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PIN
NAME
No.
ILIM
10
TS
11
QON
12
BAT
SYS
13,14
15,16
PGND
17,18
SW
BTST
19,20
21
REGN
22
PMID
23
DSEL
24
PowerPAD™
BQ25890H
SLUSCC5 – SEPTEMBER 2016
Pin Functions (continued)
TYPE ⁽¹⁾
DESCRIPTION
Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input current
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected
from ILIM pin to ground to set the maximum limit as I_INMAX = K_ILIM/R_ILIM . The actual input current limit is the
AI
lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500
mA is not support on ILIM pin.
ILIM pin can also be used to monitor input current when the voltage is below 0.8V. The input current is
proportional to the voltage on ILIM pin and can be calculated by I_IN = (K_ILIM x V_ILIM) / (R_ILIM x 0.8)
The ILIM pin function can be disabled when EN_ILIM bit is 0.
Temperature qualification voltage input.
AI
Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider
from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2
thermistor.
BATFET enable/reset control input.
When BATFET is in ship mode, a logic low of t_SHIPMODE (typical 1sec) duration turns on BATFET to exit
shipping mode. .
DI
When VBUS is not plugged-in, a logic low of t_{QON_RST} (typical 15sec) duration resets SYS (system power) by
turning BATFET off for t_{BATFET_RST} (typical 0.3sec) and then re-enable BATFET to provide full system power
reset.
The pin contains an internal pull-up to maintain default high logic
P
Battery connection point to the positive terminal of the battery pack.
The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin.
System connection point.
P
The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system
voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20uF closely to the
SYS pin.
Power ground connection for high-current power converter node.
P
Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to
ground connection of input and output capacitors of the charger. A single point connection is recommended
between power PGND and the analog GND near the IC PGND pin.
Switching node connecting to output inductor.
P
Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET.
Connect the 0.047µF bootstrap capacitor from SW to BTST.
PWM high side driver positive supply.
P
Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047 µF bootstrap
capacitor from SW to BTST.
PWM low side driver positive supply output.
P
Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7 µF (10 V rating) ceramic
capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as
bias rail of TS pin.
DO
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.
Given the total input capacitance, put 1µF on VBUS to PGND, and the rest capacitance on PMID to PGND.
Active high D+/D- multiplexer selection control.
Connect a 47-nF (6V rating) ceramic capacitor from DSEL to analog GND. The pin is normally low. During
DO input source type detection, the pin drives high to indicate the device D+/D- detection is in progress and needs
to take control of D+, D- signals. When detection is completed, the pin keeps high when DCP, MaxCharge or
HVDCP is detected. The pin returns to low when other input source type is detected
P
Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on
the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.
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