BQ25890H Datasheet, PDF (36/66 Pages) Texas Instruments – I2C Controlled Single Cell 5-A Fast Charger

BQ25890H
SLUSCC5 – SEPTEMBER 2016
www.ti.com
8.4.2 REG01
Figure 27. REG01
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. REG01
Bit
Field
7
DP_DAC[2]
6
DP_DAC[1]
5
DP_DAC[0]
4
DM_DAC[2]
3
DM_DAC[1]
2
DM_DAC[0]
1
EN_12V
0
VINDPM_OS
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
Description
D+ Pin Output Driver
000 – HiZ mode (Default)
001 – 0V (V_{0P0_VSRC} )
010 – 0.6V (V_{0P6_VSRC} )
011 – 1.2V (V_{1P2_VSRC} )
100 – 2.0V (V_{2P0_VSRC} )
101 – 2.7V (V_{2P7_VSRC} )
110 – 3.3V (V_{3P3_VSRC} )
111 – Reserved
Register bits are reset to default value when input source is plugged-in
and can be changed after D+/D- detection is completed.
D- Pin Output Driver
000 – HiZ mode (Default)
001 – 0V (V_{0P0_VSRC} )
010 – 0.6V (V_{0P6_VSRC} )
011 – 1.2V (V_{1P2_VSRC} )
100 – 2.0V (V_{2P0_VSRC} )
101 – 2.7V (V_{2P7_VSRC} )
110 – 3.3V (V_{3P3_VSRC} )
111 – Reserved
Register bits are reset to default value when input source is plugged-in
and can be changed after D+/D- detection is completed.
Enable 12V detection for MaxCharge and HVDCP
0 – Disable 12V Detection (default)
1 – Enable 12V Detection
Input Voltage Limit Offset
0 – 400mV
1 – 600mV (default)
36
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