LM3S2637 Datasheet, PDF (48/678 Pages) Texas Instruments – Stellaris® LM3S2637 Microcontroller

Architectural Overview
1.4.7
1.4.7.1
1.4.7.2
1.4.7.3
1.4.8
Additional Features
JTAG TAP Controller (see page 155)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
programming for the ARM, Stellaris, and unimplemented JTAG instructions.
System Control and Clocks (see page 168)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
Hibernation Module (see page 231)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 600
■ “Signal Tables” on page 602
■ “Operating Characteristics” on page 627
■ “Electrical Characteristics” on page 628
■ “Package Information” on page 670
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June 18, 2012
Texas Instruments-Production Data