LM3S2637 Datasheet, PDF (288/678 Pages) Texas Instruments – Stellaris® LM3S2637 Microcontroller

General-Purpose Input/Outputs (GPIOs)
8.2.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.3 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-6 on page 288
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-7 on page 288 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-6. GPIO Pad Configuration Examples
Configuration
Digital Input (GPIO)
GPIO Register Bit Value^a
AFSEL DIR
ODR
0
0
0
DEN
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
Analog Input
(Comparator)
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
X
?
?
?
?
0
?
PDR
?
?
X
X
?
?
?
?
0
?
DR2R
X
?
?
?
X
?
?
?
X
?
DR4R
X
?
?
?
X
?
?
?
X
?
DR8R
X
?
?
?
X
?
?
?
X
?
SLR
X
?
?
?
X
?
?
?
X
?
Table 8-7. GPIO Interrupt Configuration Example
Desired
Pin 2 Bit Value^a
Register
Interrupt
Event
7
6
5
4
Trigger
GPIOIS
0=edge
X
X
X
X
1=level
3
X
2
0
1
X
0
X
288
June 18, 2012
Texas Instruments-Production Data