LM3S2637 Datasheet, PDF (11/678 Pages) Texas Instruments – Stellaris® LM3S2637 Microcontroller

Stellaris^® LM3S2637 Microcontroller
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 472
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 473
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 473
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 474
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 475
Figure 14-1. I²C Block Diagram ............................................................................................. 504
Figure 14-2. I²C Bus Configuration ........................................................................................ 505
Figure 14-3. START and STOP Conditions ............................................................................. 505
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 506
Figure 14-5. R/S Bit in First Byte ............................................................................................ 506
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 506
Figure 14-7. Master Single SEND .......................................................................................... 510
Figure 14-8. Master Single RECEIVE ..................................................................................... 511
Figure 14-9. Master Burst SEND ........................................................................................... 512
Figure 14-10. Master Burst RECEIVE ...................................................................................... 513
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 514
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 515
Figure 14-13. Slave Command Sequence ................................................................................ 516
Figure 15-1. CAN Controller Block Diagram ............................................................................ 541
Figure 15-2. CAN Data/Remote Frame .................................................................................. 542
Figure 15-3. Message Objects in a FIFO Buffer ...................................................................... 551
Figure 15-4. CAN Bit Time .................................................................................................... 555
Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 588
Figure 16-2. Structure of Comparator Unit .............................................................................. 589
Figure 16-3. Comparator Internal Reference Structure ............................................................ 590
Figure 17-1. 100-Pin LQFP Package Pin Diagram .................................................................. 600
Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 601
Figure 20-1. Load Conditions ................................................................................................ 631
Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 634
Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 634
Figure 20-4. JTAG TRST Timing ............................................................................................ 634
Figure 20-5. External Reset Timing (RST) .............................................................................. 635
Figure 20-6. Power-On Reset Timing ..................................................................................... 635
Figure 20-7. Brown-Out Reset Timing .................................................................................... 636
Figure 20-8. Software Reset Timing ....................................................................................... 636
Figure 20-9. Watchdog Reset Timing ..................................................................................... 636
Figure 20-10. Hibernation Module Timing ................................................................................. 637
Figure 20-11. ADC Input Equivalency Diagram ......................................................................... 638
Figure 20-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 639
Figure 20-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 640
Figure 20-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 640
Figure 20-15. I²C Timing ......................................................................................................... 641
Figure D-1. Stellaris LM3S2637 100-Pin LQFP Package Dimensions ..................................... 670
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 672
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 673
Figure D-4. Stellaris LM3S2637 108-Ball BGA Package Dimensions ...................................... 674
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 676
June 18, 2012
11
Texas Instruments-Production Data