LM3S2637 Datasheet, PDF (13/678 Pages) Texas Instruments – Stellaris® LM3S2637 Microcontroller

Stellaris^® LM3S2637 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Revision History .................................................................................................. 24
Documentation Conventions ................................................................................ 31
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 54
Processor Register Map ....................................................................................... 55
PSR Register Combinations ................................................................................. 60
Memory Map ....................................................................................................... 68
Memory Access Behavior ..................................................................................... 70
SRAM Memory Bit-Banding Regions .................................................................... 72
Peripheral Memory Bit-Banding Regions ............................................................... 73
Exception Types .................................................................................................. 78
Interrupts ............................................................................................................ 79
Exception Return Behavior ................................................................................... 84
Faults ................................................................................................................. 85
Fault Status and Fault Address Registers .............................................................. 86
Cortex-M3 Instruction Summary ........................................................................... 88
Core Peripheral Register Regions ......................................................................... 91
Memory Attributes Summary ................................................................................ 94
TEX, S, C, and B Bit Field Encoding ..................................................................... 97
Cache Policy for Memory Attribute Encoding ......................................................... 98
AP Bit Field Encoding .......................................................................................... 98
Memory Region Attributes for Stellaris Microcontrollers .......................................... 98
Peripherals Register Map ..................................................................................... 99
Interrupt Priority Levels ...................................................................................... 124
Example SIZE Field Values ................................................................................ 152
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 156
JTAG_SWD_SWO Signals (108BGA) ................................................................. 157
JTAG Port Pins Reset State ............................................................................... 157
JTAG Instruction Register Commands ................................................................. 164
System Control & Clocks Signals (100LQFP) ...................................................... 168
System Control & Clocks Signals (108BGA) ........................................................ 168
Reset Sources ................................................................................................... 169
Clock Source Options ........................................................................................ 174
Possible System Clock Frequencies Using the SYSDIV Field ............................... 177
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 177
System Control Register Map ............................................................................. 181
RCC2 Fields that Override RCC fields ................................................................. 196
Hibernate Signals (100LQFP) ............................................................................. 232
Hibernate Signals (108BGA) .............................................................................. 233
Hibernation Module Register Map ....................................................................... 239
Flash Protection Policy Combinations ................................................................. 253
User-Programmable Flash Memory Resident Registers ....................................... 256
Flash Register Map ............................................................................................ 256
GPIO Pins With Non-Zero Reset Values .............................................................. 279
GPIO Pins and Alternate Functions (100LQFP) ................................................... 279
GPIO Pins and Alternate Functions (108BGA) ..................................................... 280
GPIO Signals (100LQFP) ................................................................................... 281
June 18, 2012
13
Texas Instruments-Production Data