LM3S2637 Datasheet, PDF (351/678 Pages) Texas Instruments – Stellaris® LM3S2637 Microcontroller

Stellaris^® LM3S2637 Microcontroller
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
12
reserved
RO
RO
RO
0
0
0
11
10
9
8
7
CBECINT CBMCINT TBTOCINT
RO
W1C
W1C
W1C
RO
0
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RTCCINT CAECINT CAMCINT TATOCINT
RO
W1C
W1C
W1C
W1C
0
0
0
0
0
Bit/Field
31:11
10
Name
reserved
CBECINT
Type
RO
W1C
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
9
CBMCINT
W1C
0
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
8
TBTOCINT
W1C
0
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
0 The interrupt is unaffected.
1 The interrupt is cleared.
7:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2012
351
Texas Instruments-Production Data