DS90UB948-Q1_16 Datasheet, PDF (39/88 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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Device Functional Modes (continued)
V_DD33
R1
VR1
R2
MODE_SEL[1:0]
Deserializer
DS90UB948-Q1
SNLS477A – OCTOBER 2014 – REVISED JANUARY 2016
Figure 31. MODE_SEL[1:0] Connection Diagram
# Ideal Ratio
V_R1/VDD33
1
0
2
0.169
3
0.230
4
0.295
5
0.376
6
0.466
7
0.556
8
0.801
Target V_R1
(V)
0
0.559
0.757
0.974
1.241
1.538
1.835
2.642
Table 8. Configuration Select (MODE_SEL0)
Suggested
Resistor R1 kΩ
(1% tol)
Open
232
107
113
113
107
90.9
45.3
Suggested
Resistor R2 kΩ
(1% tol)
40.2 or Any
47.5
31.6
47.5
68.1
93.1
113
182
MAP_SEL OUTPUT_MODE
[1:0]
0
00
0
01
0
10
0
11
1
00
1
01
1
10
1
11
Output
Mode
Dual OLDI output
Dual SWAP output
Single OLDI output
Replicate
Dual OLDI output
Dual SWAP output
Single OLDI output
Replicate
# Ideal Ratio
V_R1/VDD33
1
0
2
0.169
3
0.230
4
0.295
5
0.376
6
0.466
7
0.556
8
0.801
Target V_R1
(V)
0
0.559
0.757
0.974
1.241
1.538
1.835
2.642
Table 9. Configuration Select (MODE_SEL1)
Suggested
Suggested
Resistor R1 kΩ Resistor R2 kΩ
(1% tol)
(1% tol)
Open
40.2 or Any
232
47.5
107
31.6
113
47.5
113
68.1
107
93.1
90.9
113
45.3
182
Repeater
0
0
0
0
1
1
1
1
MODE
00
01
10
11
00
01
10
11
High Speed
Back Channel
5 Mbps
5 Mbps
20 Mbps
20 Mbps
5 Mbps
5 Mbps
20 Mbps
20 Mbps
Input
Mode
STP
Coax
STP
Coax
STP
Coax
STP
Coax
8.4.3 OpenLDI Output Frame and Color Bit Mapping Select
The DS90UB948-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different
mapping schemes, shown in Figure 32 and Figure 33. Each frame corresponds to a single pixel clock (PCLK)
cycle. The LVDS clock output from CLK1± and CLK2± follows a 4:3 duty cycle scheme, with each 28-bit pixel
frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is
controlled by MODE_SEL0 pin or by Register (Table 11).
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