DS90UB948-Q1_16 Datasheet, PDF (1/88 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UB948-Q1
SNLS477A – OCTOBER 2014 – REVISED JANUARY 2016
DS90UB948-Q1 1080p FPD-Link III to OpenLDI Deserializer
1 Features
•1 Supports Pixel Clock Frequency up to 170 MHz
for WUXGA (1920x1200) and 1080p60
Resolutions with 24-bit Color Depth
• 1-lane or 2-lane FPD-Link III Interface with De-
skew Capability
• Single or Dual OpenLDI (LVDS) Transmitter
– Single Channel: Up to 96 MHz Pixel Clock
– Dual Channel: Up to 170 MHz Pixel Clock
– Configurable 18-bit RGB or 24-bit RGB
• High Speed GPIO up to 2.0 Mbps
• Supports up to 15 meters of cable with automatic
temperature and aging compensation
• SPI Control Interfaces up to 3.3 Mbps
• I²C (Master/Slave) with 1 Mbps Fast-mode Plus
• Adaptive Receive Equalization
• Image Enhancement (White Balance and
Dithering)
• Supports 7.1 Multiple I2S (4 data) Channels
• Backward Compatible to DS90UB925/925AQ-Q1
and DS90UB927Q-Q1 FPD-Link III Serializers
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
2 Applications
• Automotive Infotainment:
– Central Information Displays
– Rear Seat Entertainment Systems
– Digital Instrument Clusters
3 Description
The DS90UB948-Q1 is a FPD-Link III Deserializer
which, in conjunction with the DS90UB949/947/929-
Q1 Serializers, converts 1-lane or 2-lane FPD-Link III
streams into a FPD-Link (OpenLDI) interface. The
Deserializer is capable of operating over cost-
effective 50Ω single-ended coaxial or 100Ω
differential shielded twisted-pair (STP) cables. It
recovers the data from one or two FPD-Link III serial
streams and translates it into dual pixel FPD-Link (8
LVDS data lanes + clock) supporting video
resolutions up to WUXGA and 1080p60 with 24-bit
color depth. This provides a bridge between HDMI
enabled sources such as GPUs to connect to existing
LVDS displays or Application Processors.
The FPD-Link III interface supports video and audio
data transmission and full duplex control, including
I²C and SPI communication, over the same
differential link. Consolidation of video data and
control over two differential pairs reduces the
interconnect size and weight and simplifies system
design. EMI is minimized by the use of low voltage
differential signaling, data scrambling, and
randomization. In backward compatible mode, the
device supports up to WXGA and 720p resolutions
with 24-bit color depth over a single differential link.
The device automatically detects the FPD-Link III
channels and provides a clock alignment and de-
skew functionality without the need for any special
training patterns. This ensures skew phase tolerance
from mismatches in interconnect wires such as PCB
trace routing, cable pair-to-pair length differences,
and connector imbalances.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UB948-Q1
WQFN NKD (64) 9.00 mm x 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Applications Diagram
HDMI
or
DP++
VDDIO
(1.8V)
1.8V 1.1V
Mobile
Device
or
Graphics
Processor
IN_CLK-/+
IN_D0-/+
IN_D1-/+
IN_D2-/+
CEC
DDC
HPD
DOUT0+
DOUT0-
DOUT1+
DOUT1-
DS90UB949-Q1
Serializer
I2C
IDx
D_GPIO
(SPI)
1
FPD-Link III
2 lanes
I2C
IDx
D_GPIO
(SPI)
3.3V 1.2V
VDDIO
(3.3 / 1.8V)
FPD-Link
(Open LDI)
RIN0+
RIN0-
RIN1+
RIN1-
DS90UB948-Q1
Deserializer
CLK1+/-
D0+/-
D1+/-
D2+/-
D3+/-
CLK2+/-
D4+/-
D5+/-
D6+/-
D7+/-
LVDS
Display
1080p60
or Graphic
Processor
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.