DS90UB948-Q1_16 Datasheet, PDF (22/88 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UB948-Q1
SNLS477A – OCTOBER 2014 – REVISED JANUARY 2016
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8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, I2C,
GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 18 illustrates the serial stream per clock
cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 18. FPD-Link III Serial Stream
The DS90UB948-Q1 supports clocks in the range of 25 MHz to 96 MHz over a 1-lane, or 50MHz to 170MHz
over 2-lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) or 2.975 Gbps
maximum per lane (875 Mbps minimum) respectively.
8.3.2 Low Speed Back Channel Data Transfer
The Low-Speed Backward Channel provides bidirectional communication between the display and host
processor. The information is carried from the deserializer to the serializer as serial frames. The back channel
control data is transferred over both serial links along with the high-speed forward data, DC balance coding and
embedded clock information. This architecture provides a backward path across the serial link together with a
high speed forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information
with 5 or 20 Mbps line rate (configured by MODE_SEL1).
8.3.3 FPD-Link III Port Register Access
Since the DS90UB948-Q1 contains two ports, some registers need to be duplicated to allow control and
monitoring of the two ports. To facilitate this, PORT1_SEL and PORT0_SEL bits (0x34[1:0]) register controls
access to the two sets of registers. Registers that are shared between ports (not duplicated) will be available
independent of the settings in the PORT_SEL register.
Setting the PORT1_SEL and PORT0_SEL bit will allow a read of the register for the selected port. If both bits are
set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing simultaneous
writes to both ports if both select bits are set.
8.3.4 Oscillator Output
The deserializer provides an optional CLK[2:1]± output when the input clock (serial stream) has been lost. This is
based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable). See
Table 11.
8.3.5 Clock and Output Status
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is tri-state or LOW
(depending on the value of the OUTPUT ENABLE setting). After the deserializer completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the LVCMOS and LVDS outputs. The State of the outputs is based on the OUTPUT
ENABLE and OUTPUT SLEEP STATE SELECT register settings. See register 0x02 in Table 11.
Serial
Input
X
X
X
PDB
L
H
H
Inputs
OUTPUT ENABLE
Reg 0x02 [7]
X
L
L
Table 2. Output State Table
OUTPUT SLEEP
STATE SELECT
Reg 0x02 [4]
X
L
H
LOCK
Z
L
L or H
Outputs
PASS
Data
GPIO / D_GPIO
I2S
Z
Z
L
L
Z
Z
D[7:0] /
CLK[2:1]
Z
L
Z
22
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