DS90UB948-Q1_16 Datasheet, PDF (16/88 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UB948-Q1
SNLS477A – OCTOBER 2014 – REVISED JANUARY 2016
Timing Diagrams and Test Circuits (continued)
EW
VOD (+)
RIN
(Diff.)
EH
0V
EH
t_BIT (1 UI)
Figure 2. CML Output Driver
VOD (-)
t_CLH
80%
20%
t_CHL
Figure 3. LVCMOS Transition Times
V_DDIO
GND
RIN[1:0]
DCA, DCB
CLK[2:1]
START
STOP
BIT SYMBOLN BIT
START
STOP
BIT SYMBOLN+1 BIT
START
STOP
BIT SYMBOLN+2 BIT
START
STOP
BIT SYMBOLN+3 BIT
t_DD
D[7:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Latency Delay
PDB
VILmax
RIN[1:0]
LOCK
PASS
CLK[2:1]
D[7:0]
X
t_TPDD
Z
Z
Z
Z
Figure 5. FPD-Link & LVCMOS Power Down Delay
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