DS90UB948-Q1_16 Datasheet, PDF (37/88 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

www.ti.com
DS90UB948-Q1
SNLS477A – OCTOBER 2014 – REVISED JANUARY 2016
Device Functional Modes (continued)
8.4.1.4 2-lane FPD-Link III Input, Single Link OpenLDI Output
In this configuration the PCLK rate embedded within 2-lane FPD-Link III frame can range from 50 MHz to 170
MHz, resulting in a link rate of 875 Mbps (35 bit * 25 MHz) to 2.975 Gbps (35 bit * 85 MHz). Each LVDS data
lane will operate at a speed of 7 bits per LVDS clock cycle; resulting in a serial line rate of 350 Mbps to 1190
Mbps. CLK1 will operate at the twice the rate as PCLK with a duty cycle ratio of 57:43.
8.4.1.5 1-lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
Same as 1-lane FPD-Link III Input, Single Link OpenLDI Output mode and duplicates the LVDS signal on D4 to
D7 outputs.
8.4.2 MODE_SEL[1:0]
Possible configurations are shown in Figure 30. These are described above (Configuration Select
MODE_SEL[1:0]).
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: DS90UB948-Q1
Submit Documentation Feedback
37