TLC320AD55 Datasheet, PDF (35/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

Appendix A
Register Set
Data bits D12 through D8 in the secondary serial communication contain the address of the register, and
data bits D7 through D0 contain the data that is to be written to the register. Data bit D13 determines a read
or write cycle to the addressed register. When data bit D13 is low, a write cycle is selected.
The following table shows the register map:
Table A– 1. Register Map
REGISTER NO. D15 D14 D13 D12 D11 D10 D9 D8 REGISTER NAME
0
00000000
No operation
1
00000001
Control 1
2
00000010
Control 2
3
00000011
Fk divide
4
00000100
Fsclk divide
5
00000101
Control 3
Table A– 2. Control 1 Register
D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
1 – – – – – – – Software reset
0 – – – – – – – Software reset not asserted
– 1 – – – – – – Software power down (analog and filters)
– 0 – – – – – – Software power down (not asserted)
– – 1 – – – – – Select AUXP and AUXM
– – 0 – – – – – Select INP and INM
– – – 0 0 – – – Analog output gain = 1
– – – 0 1 – – – Analog output gain = 1/2
– – – 1 0 – – – Analog output gain = 1/4
– – – 1 1 – – – Analog output gain = 0 (squelch)
– – – – – 1 – – Analog loopback asserted
– – – – – 0 – – Analog loopback not asserted
– – – – – – 1 – Digital loopback asserted
– – – – – – 0 – Digital loopback not asserted
– – – – – – – 1 16-bit mode (hardware secondary requests)
– – – – – – – 0 Not 16-bit mode (software secondary requests)
Default register value: 00000000
The software reset is a one-shot operation and this bit is cleared to zero after reset. It is not necessary to
write a zero to end the master reset operation.
A–1