TLC320AD55 Datasheet, PDF (22/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

Table 3–1. Least-Significant-Bit Control Function
CONTROL BIT D0
0
1
CONTROL BIT FUNCTION
No operation (no-op)
Secondary communication request
On the falling edge of the next FS, D15 through D1 is input to DIN or D15 through D0 is output to DOUT.
When a secondary communication request is made, FS goes low for 32 FCLKs (see Fk divide register,
Appendix A) after the beginning of the primary frame.
Communication Frame 1 (CF1)
Communication Frame 2 (CF2)
FS _Primary
Secondary
Primary
No Secondary
Request
FC _{ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ8 ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ}
DOUT
SCLKs
(Secondary
Read)
ADC Data
Out
ADC Data
Out
Register
Data
DOUT
(Secondary
ADC Data
Out
All Bits 0
ADC Data
Out
Write)
DIN
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ _(Secondary DAC DataIn
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ^{Read or Write)}
Secondary
Update
DAC Data In
16 SCLKs
16
SCLKs
16 SCLKs
32 FCLKs†
64 FCLKs†
64 FCLKs†
(128 SCLKs when Fk = Fsclk)‡
† _{See Fk divide register in Appendix A.}
‡ _{For a selected MCLK, Fk and Fsclk: SCLK = 2 Fk/Fsclk × FCLK}
Figure 3– 5. Hardware FC Secondary Request
(Phone Mode Disabled)
3–4