TLC320AD55 Datasheet, PDF (16/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

2.2.1.3 Software and Hardware Power-Down
Given the definitions above, the software-programmed power-down condition is cleared by programming
the software bit (control 1 register bit 6) to a 0 or is cleared by cycling the power to the device, bringing
PWRDWN low, or bringing RESET low (see Figure 2–2).
PWRDWN removes power to the entire chip. The software-programmable, power-down bit only removes
power from the analog section of the chip, which allows a software power-up function. Cycling the
power-down terminal from high to low and back to high resets all flip-flops and latches that are not externally
programmed, thereby preserving the register contents with the exception that the software power-down bit
is cleared.
When PWRDWN is not being used, it should be tied high [V_DD(ADC) is preferred].
PWRDWN
Digital Circuitry
Power-Down
Analog Circuitry
Power-Down
Clear
(For Control
Register 1,
Bit 6)
Bit 6 is Programmed
Through a Secondary
Write Operation
Internal TLC320AD55C
Figure 2– 2. Internal Power-Down Logic
2.2.2 Master Clock Circuit
The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK [SCLK = MCLK/(Fsclk × 2), Fsclk = 1,2,3,...,256] in order
to provide clocking of the serial communications between the device and a digital signal processor (DSP).
The sample rate of the data paths is set as MCLK/(Fk × 256). Fk and Fsclk are programmable register values
used as divisors of MCLK. The default value for the Fk and Fsclk register is 8 (decimal).
2.2.3 Data Out (DOUT)
DOUT is taken from the high-impedance state by the falling edge of the frame-sync signal. The most
significant data bit then appears on DOUT.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK (internal or external) after
the falling edge of the frame-sync signal. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/ write (R / W) bit with the eight MSBs set to zero (see the serial communications section). When a
register read is not requested, the secondary word is all zeroes.
2.2.4 Data In (DIN)
In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 3 Serial Communications).
2–4