TLC320AD55 Datasheet, PDF (31/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

4.4.8 Power Supplies, V_DD(ADC) = V_DD(DAC) = DV_DD = 5 V, No Load (unless
otherewise noted)
PARAMETER
TEST CONDITIONS MIN TYP MAX
IDD (ADC) Power supply current, ADC
Operating
Power-down
12
20
400
IDD (DAC) Power supply current, DAC
Operating
Power-down
16
24
2.5
IDD (Digital) Power supply current, digital
Operating
Power-down
2
6
300
PD
Power dissipation
Operating
Power-down
150 250
16
30
UNIT
mA
µA
mA
mA
mA
µA
mW
4.4.9 Timing Requirements (see Notes 9 and 10)
PARAMETER
TEST CONDITIONS
td1 Delay time, SCLK↑ to FS↓
td2 Delay time, SCLK↑ to DOUT
tsu Setup time, DIN before SCLK↓
th
Hold time, DIN after SCLK↓
CL = 20 pF
ten Enable time, FS↓ to DOUT
tdis Disable time, FS↑ to DOUT Hi-Z
td3 Delay time MCLK↓ to SCLK↑
NOTES: 9. Refer to Figure 3–1 for timing diagram.
10. When FS occurs after SCLK, it shortens the MSB (D15) duration.
MIN TYP MAX UNIT
10
15
6
20
20
20 ns
10
25
20
25
50
4–5