TLC320AD55 Datasheet, PDF (27/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

4 Specifications
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted)^†
Supply voltage range, DV_DD, V_DD(ADC, DAC)(see Note 1) . . . . . . . . . . –0.3 V to 6.5 V
Output voltage range, DOUT, FS, SCLK, FLAG 0, FLAG 1 . . . – 0.3 V to DV_DD + 0.3 V
Output voltage range, OUTP, OUTM . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V_DD + 0.3 V
Input voltage range, DIN, PWRDWN, RESET, ALT DATA,
MCLK, FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DV_DD + 0.3 V
Input voltage range, INP, INM, AUXP, AUXM . . . . . . . . . . . . . . . . – 0.3 V to V_DD + 0.3 V
Case temperature for 10 seconds, T_C: DW package . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These}
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS(DAC) for DAC channel measurements and VSS(ADC) for ADC
channel measurements.
4.2 Recommended Operating Conditions
Supply voltage, VDD(ADC, DAC)
Analog signal input voltage, VI
Load resistance for OUTP and OUTM, RL
Load capacitance for OUTP and OUTM, CL
ADC or DAC conversion rate (Nyquist)
Operating free-air temperature, TA
Differential, (INP – INM) peak,
for full scale operation
MIN NOM MAX UNIT
4.5
5.5 V
6V
0.3
10
kΩ
100 pF
8
kHz
0
70 °C
4.3 Recommended Operating Conditions, DV_DD = 5 V
MIN NOM
Supply voltage, DVDD
High-level input voltage, VIH
Low-level input voltage, VIL
MCLK frequency (see Note 2), duty cycle = 50 ± 10%
4.5
2
16.384
NOTE 2: The default state for an 8 kHz conversion rate requires a 16.384 MHz MCLK frequency.
MAX
5.5
0.8
UNIT
V
V
V
MHz
4–1