TLC320AD55 Datasheet, PDF (23/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

In Figure 3–6, FC hardware terminal 15 is left in its nonasserted state (0). FC is asserted through software
by embedding an asserted high level (1) in the LSB of the 16-bit primary word. This is possible when not
in 16-bit mode (control 1 register bit 2 = 0) because the user is using only 15 bits of DAC information.
Communication Frame 1 (CF1)
Communication Frame 2 (CF2)
FS _Primary
Secondary
Primary
No Secondary
Request
FC
0
DIN
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ^(Secondary
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ^{Read or Write)}
D15–D1 D0 = 1
DAC Data In
Secondary
Update
D15–D1 D0 = 0
DAC Data In
DOUT
Software FC Bit
8 SCLKs
(Secondary
Read)
ADC Data
Out
ADC Data
Out
Register
Data
DOUT
(Secondary
Write)
ADC Data
Out
All Bits 0
ADC Data
Out
16 SCLKs
16 SCLKs
16 SCLKs
32 FCLKs†
64 FCLKs†
64 FCLKs†
† _{See Fk divide register in Appendix A.}
NOTE A: For a read cycle, the last 8 bits are don’t care.
Figure 3– 6. Software FC Secondary Request (Phone Mode Disabled)
Table 3–2 shows the secondary communications format. D13 is the R/W bit, the read/not-write bit.
D12 through D8 are address bits. The register map is specified in the register set section in Appendix A.
D7 through D0 are data bits. The data bits are values for the specified register addressed by data bits D12
through D8.
Table 3– 2. Secondary Communication Data Format
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X R/W A
A
A
A
A
D
D
D
D
D
D
D
D
3.3 Conversion Rate Versus Serial Port
The SCLK frequency can be programmed independently from the FCLK frequency. This can create a
problem with the interpretation of the serial port data. The serial port is designed to initiate a primary
communication every 64 SCLKs. There must be an integer number of SCLKs ≥ 40 per sample period. Two
examples follow to demonstrate the possible output of the serial port. SCLK must be fast enough to collect
all data from each frame.
Example 1: MCLK = 4.096 MHz, sample rate = 8 kHz, 8 kHz = MCLK/ (Fk × 256), set Fk = 2,
SCLK = MCLK/ (Fsclk × 2), set Fsclk = 2, SCLK = 1.024 MHz. With this configuration,
SCLK = sample rate × 128. Therefore, each primary communication is a valid sample.
3–5