TLC320AD55 Datasheet, PDF (20/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

Figure 3–1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The
timing sequence for this operation is as follows:
1. The TLC320AD55C takes FS low.
2. One 16-bit word is transmitted from the ADC (DOUT) and one 16-bit word is received for the DAC
(DIN).
ÎÎÎ 3. The TLC320AD55C takes FS high.
td3
VIH
MCLK
VIL
VOH
SCLK
0th
1st
td1
FS
2nd
14th
ÎÎÎÎ_td2
15th
16th
VOL
VOH
VOL
ten
tdis
DOUT
D15
D14
...D2
D1
D0
In 16-Bit Mode:
ÏÏÏÏÏÏ _DIN
tsu
D15
D14
...D2
MSB
th
D1 D0ÏÏÏÏÏÏÏÏÏÏ
LSB
tsu
In 16-Bit Mode:
ÏÏÏÏÏÏ ^DIN
D15
MSB
th
D14
...D2
D1
LSB
FC _{ÏÏÏÏÏÏÏÏÏÏ}
Figure 3–1. Primary Serial Communication Timing
When a secondary request is made through the LSB of the DAC data word (16-bit mode), the format shown
in Figure 3–2 is used:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
15-bit DAC
2s-complement format
16-bit ADC
2s-complement format
D0
control
Figure 3– 2. DAC and ADC Word Lengths
3–2