TLC320AD55 Datasheet, PDF (13/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

2 Functional Description
2.1 Device Functions
The following sections describe the functions of the device.
2.1.1 Operating Frequencies
The sampling (conversion) frequency is derived from the master clock (MCLK) input by the following
equation:
+ + fs
Sampling (conversion) frequency
MCLK frequency
(Fk register value) 256
The inverse is the time between the falling edges of two successive primary frame-synchronization signals
and it is the conversion period.
The input and output data clock (SCLK) is given by:
+ ^{MCLK frequency}
SCLK frequency _{(Fsclk register value) 2}
2.1.2 ADC Signal Channel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data.
The ADC converts the signal into discrete output digital words in 2s-complement format, corresponding to
the analog-signal value at the sampling time. These 16-bit digital words, representing sampled values of
the analog input signal, are clocked out of the serial port, DOUT, during the frame-sync interval (one word
for each primary communication interval). During secondary communications, the data previously
programmed into the registers can be read out with the appropriate register address, and the read bit set
to 1. When a register read is not requested, all 16 bits are 0 in the secondary word.
2.1.3 DAC Signal Channel
DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
voltage by the DAC and then passed through a (sin x)/x correction circuit and a smoothing filter. An output
buffer with three software-programmable gains (0 dB, – 6 dB, and – 12 dB) drives the differential outputs
OUTP and OUTM. A squelch mode can also be programmed for the output buffer. During secondary
communications, the configuration program data are read into the device control registers.
2.1.4 Serial Interface
The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval,
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a one. In addition, SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 3–1.
2.1.5 Register Programming
All register programming occurs during secondary communications, and data are latched and valid on the
rising edge of the frame-sync signal. When the default value for a particular register is desired, that register
does not need to be addressed during secondary communications. The no-op command addresses the
no-op register (register 0), and register programming does not take place during this communication.
2–1