TLC320AD55 Datasheet, PDF (12/41 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

1.7 Register Functional Summary
There are six data and control registers that are used as follows:
Register 0
The No-op register. The 0 register allows secondary requests without altering any other
register.
Register 1 The control 1 register. The data in this register controls:
• The software reset
• The software power-down
• Selection of the normal or auxiliary analog inputs
• The output amplifier gain (1, 1/2, 1/4, or squelch)
• Selection of the analog loopback
• Selection of the digital loopback
• 16-bit or 15-bit mode of operation
Register 2 The control 2 register. The data in this register:
• Contains the output flag indicating a decimator FIR filter overflow
• Contains Flag 0 and Flag 1 output values for use in the phone mode
• Selects the phone mode
• Selects or bypasses the decimation FIR filter
Register 3
Register 4
Register 5
• Selects or bypasses the interpolater FIR filter
The Fk divide register. This register controls the filter clock rate and the sample period.
The Fsclk divide register. This register controls the shift (data) clock rate.
The control 3 register. This register enables and disables the DAC reference.
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