BQ25120_16 Datasheet, PDF (35/68 Pages) Texas Instruments – Highly Integrated Battery Charge Management Solution

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BQ25120, BQ25121
SLUSBZ9B – AUGUST 2015 – REVISED MAY 2016
9.6.2 Faults and Faults Mask Register
Memory location 0x01h, Reset State: xxxx 0000 (bq25120)
Figure 24. Faults and Faults Mask Register
7 (MSB)
6
5
4
3
2
1
0 (LSB)
x
x
x
x
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Faults and Faults Mask Register
Bit Field
B7 (MSB) VIN_OV
B6
VIN_UV
B5
BAT_UVLO
B4
B3
B2
B1
B0 (LSB)
BAT_OCP
VIN_OV_M
VIN_UV_M
BAT_UVLO_M
BAT_OCP_M
Type
R
R
Reset
x
x
R
x
R
x
R/W
0
R/W
0
R/W
0
R/W
0
Description
1 - V_IN overvoltage fault. VIN_OV continues to show fault after
an I²C read as long as OV exists
1 - V_IN undervoltage fault. VIN_UV is set when the input falls
below V_SLP. VIN_UV fault shows only one time. Once read,
VIN_UV clears until the the UVLO event occurs.
1 – BAT_UVLO fault. BAT_UVLO continues to show fault after
an I²C read as long as BAT_UVLO conditions exist.
1 – BAT_OCP fault. BAT_OCP is cleared after I²C read.
1 – Mask V_IN overvoltage fault
1 – Mask V_IN undervoltage fault
1 – Mask BAT UVLO fault
1 – Mask BAT_OCP fault
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