BQ25120_16 Datasheet, PDF (11/68 Pages) Texas Instruments – Highly Integrated Battery Charge Management Solution

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BQ25120, BQ25121
SLUSBZ9B – AUGUST 2015 – REVISED MAY 2016
Electrical Characteristics (continued)
Circuit of , V_(UVLO) < V_IN < V_(OCP) and V_IN > V_(BAT) + V_(SLP), T_J = –40 to 85°C and T_J = 25°C for typical values (unless otherwise
noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T_HYS
Thermal hysteresis
t_{DGL_SHTDW} Deglitch time, Thermal
N
shutdown
I2C INTERFACE
V_IN > V_UVLO
T_J rising above T_SHTDWN
11
°C
4
µs
I²C Bus Specification
standard and fast mode
frequency support
100
400
kHz
V_IL
V_IH
V_IH
V_OL
I_BIAS
Input low threshold level V_PULLUP = 1.1 V, SDA and SCL
Input high threshold level V_PULLUP = 1.1 V, SDA and SCL
Input high threshold level V_PULLUP = 3.3 V, SDA and SCL
Output low threshold level IL = 5mA, sink current, V_PULLUP = 1.1 V
High-Level leakage
current
V_PULLUP = 1.8V, SDA and SCL
0.825
2.475
0.275
V
V
V
0.275
V
1
µA
INT, PG, and RESET OUTPUT (Open Drain)
V_OL
Low level output
threshold
Sinking current = 5 mA
I_IN
V_{IN(BAT_DEL}
TA)
Bias current into pin
Input voltage above
VBAT where PG sends
two 128 µs pulses each
minute to signal the host
of the input voltage status
Pin is high impedance, I_OUT = 0 mA
V_UVLO < V_IN < V_OVP
0.25 x
V_(SYS)
V
0
12
nA
0.825
1
1.15
V
INPUT PIN (CD LSCTRL)
V_{IL(/CD_LSCT Input low threshold}
RL)
V_{IH(/CD_LSC Input high threshold}
TRL)
R_PULLDOWN/ Internal pull-down
CD
resistance
R_(LSCTRL)
Internal pull-down
resistance
V_(PULLUP) = 1V
V_(PULLUP) = 1V
0.25
V
0.75
V
900
kΩ
2
MΩ
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