BQ25120_16 Datasheet, PDF (32/68 Pages) Texas Instruments – Highly Integrated Battery Charge Management Solution

BQ25120, BQ25121
SLUSBZ9B – AUGUST 2015 – REVISED MAY 2016
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Programming (continued)
To avoid I²C hang-ups, a timer (t_I2CRESET) runs duringI²C transactions. If the SDA line is held low longer than
t_I2CRESET, any additional commands are ignored and the I²C engine is reset. The timeout is reset with START and
repeated START conditions and stops when a valid STOP condition is sent.
9.5.2 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 19. All I²C-compatible devices should
recognize a start condition.
DATA
CLK
S
START Condition
Figure 19. Start Stop Condition
P
STOP Condition
The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on
the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the
SDA line to be stable during the entire high period of the clock pulse (see Figure 20). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see Figure 21) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 20. Bit Transfer on the Serial Interface
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