BQ25120_16 Datasheet, PDF (18/68 Pages) Texas Instruments – Highly Integrated Battery Charge Management Solution

BQ25120, BQ25121
SLUSBZ9B – AUGUST 2015 – REVISED MAY 2016
www.ti.com
9.3 Feature Description
9.3.1 Ship Mode
Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET
until V_IN > V_UVLO or the MR button is depressed for t_WAKE1 and released. To enter Ship Mode, CD must be pulled
high. If the EN_SHIPMODE is written to a 1 while the input is connected, it must first be removed to enter ship
mode. This allows the end product with minimal load on the battery, and the end user will enable the device by
plugging it into the adapter or by toggling the MR button or both depending on the register settings. The battery
voltage must be above the maximum programmable BUVLO threshold in order to exit Ship mode. The
EN_SHIPMODE bit can be cleared using the I²C interface as well while the input is valid. The following list shows
the events that are active during Ship Mode:
1. VIN_UV Comparator
2. MR Input (No clock or delay in this mode for lowest power consumption)
9.3.2 High Impedance Mode
High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode
the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are
in a low power or sleep state.The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the
LS/LDO output has been enabled through I²C prior to entering Hi-Z mode, it will stay enabled. The CD pin is
used to put the device in a high-impedance mode when battery is present and V_IN < V_UVLO. Drive CD high to
enable the device and enter active battery operation when V_IN is not valid. When the HZ_MODE bit is written by
the host, the I²C interface is disabled if only battery is present. To resume I²C, the CD pin must be toggled. The
functionality is shown in Table 1.
CD, State
L
H
Table 1. CD, State Table
V_IN < V_UVLO
Hi-Z
Active Battery
V_IN > V_UVLO
Charge Enabled
Charge Disabled
9.3.3 Active Battery Only Connected
When the battery above V_BATUVLO is connected with no input source, the battery discharge FET is turned on.
After the battery rises above V_BATUVLO and the deglitch time is reached, the SYS output starts to rise. The current
from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit limit is
reached for the deglitch time (t_{DGL_SC}), the battery discharge FET is turned off for the recovery time (t_{REC_SC}).
After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not, the FET
turns off and the process repeats until the short is removed. This process protects the internal FET from over
current. During this event PMID will likely droop and cause SYS to go out of regulation. After SYS recovers, it is
recommended that the host read the Faults Register to determine the cause of the event.
To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. Deeper
discharge of the battery enables longer times between charging, but may shorten the battery life. The BATUVLO
is adjustable with a fixed 100-mV hysteresis.
If a valid V_IN is connected during active battery mode, V_IN > V_UVLO, the supplement and battery discharge FET is
turned on when the battery voltage is above the minimum V_BATUVLO.
Drive CD high or write the CE register to disable charge when V_IN > V_UVLO is present. CD is internally pulled
down. When exiting this mode, charging resumes if V_IN is present, CD is low and charging is enabled.
All HOST interfaces (CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches
the programmed level.
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