BQ25120_16 Datasheet, PDF (33/68 Pages) Texas Instruments – Highly Integrated Battery Charge Management Solution

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Programming (continued)
BQ25120, BQ25121
SLUSBZ9B – AUGUST 2015 – REVISED MAY 2016
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
START
Condition
1
2
8
Figure 21. Acknowledge on the I²C Bus
9
Clock Pulse for
Acknowledgement
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 22). This releases the bus and stops the communication
link with the addressed slave. All I²C compatible devices must recognize the STOP condition. Upon the receipt of
a STOP condition, all devices know that the bus is released, and wait for a START condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I²C logic from remaining in an incorrect state. Attempting to read data from register addresses
not listed in this section results in 0xFFh being read out.
Recognize START or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Recognize STOP or
REPEATED START
Condition
P
SDA
MSB
Acknowledgement
Sr
Signal From Slave
Address
SCL
S
or
Sr
R/W
ACK
Sr
ACK
or
P
Figure 22. Bus Protocol
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