DRV2605L Datasheet, PDF (33/69 Pages) Texas Instruments – DRV2605L 2 to 5.2 V Haptic Driver for LRA and ERM With Effect Library and Smart-Loop Architecture

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DRV2605L
SLOS854C – MAY 2014 – REVISED SEPTEMBER 2014
8.6 Register Map
REG
NO.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
DEFAULT
0xE0
0x40
0x00
0x01
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x05
0x19
0xFF
0x19
0xFF
0x3E
0x8C
0x0C
0x6C
0x36
0x93
0xF5
0xA0
0x20
0x80
0x33
0x00
0x00
Table 3. Register Map Overview
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
DEVICE_ID[2:0]
Reserved
DIAG_RESULT
Reserved
DEV_RESET
STANDBY
Reserved
RTP_INPUT[7:0]
Reserved
HI_Z
Reserved
LIBRARY_SEL[2]
WAIT1
WAV_FRM_SEQ1[6:0]
WAIT2
WAV_FRM_SEQ2[6:0]
WAIT3
WAV_FRM_SEQ3[6:0]
WAIT4
WAV_FRM_SEQ4[6:0]
WAIT5
WAV_FRM_SEQ5[6:0]
WAIT6
WAV_FRM_SEQ6[6:0]
WAIT7
WAV_FRM_SEQ7[6:0]
WAIT8
WAV_FRM_SEQ8[6:0]
Reserved
ODT[7:0]
SPT[7:0]
SNT[7:0]
BRT[7:0]
Reserved
ATH_PEAK_TIME[1:0]
ATH_MIN_INPUT[7:0]
ATH_MAX_INPUT[7:0]
ATH_MIN_DRIVE[7:0]
ATH_MAX_DRIVE[7:0]
RATED_VOLTAGE[7:0]
OD_CLAMP[7:0]
A_CAL_COMP[7:0]
A_CAL_BEMF[7:0]
N_ERM_LRA
FB_BRAKE_FACTOR[2:0]
LOOP_GAIN[1:0]
STARTUP_BOOST
Reserved
AC_COUPLE
DRIVE_TIME[4:0]
BIDIR_INPUT
BRAKE_STABILIZER
SAMPLE_TIME[1:0]
BLANKING_TIME[1:0]
NG_THRESH[1:0]
ERM_OPEN_LOOP
SUPPLY_COMP_DIS
DATA_FORMAT_RTP LRA_DRIVE_MODE
ZC_DET_TIME[1:0]
AUTO_CAL_TIME[1:0]
Reserved
OTP_STATUS
AUTO_OL_CNT[1:0]
LRA_AUTO_OPEN_LOOP PLAYBACK_INTERVAL
BLANKING_TIME[3:2]
Reserved
OL_LRA_PERIOD[6:0]
VBAT[7:0]
LRA_PERIOD[7:0]
BIT 1
OVER_TEMP
MODE[2:0]
LIBRARY_SEL[1]
BIT 0
OC_DETECT
LIBRARY_SEL[0]
GO
ATH_FILTER[1:0]
BEMF_GAIN[1:0]
IDISS_TIME[1:0]
N_PWM_ANALOG
LRA_OPEN_LOOP
Reserved
OTP_PROGRAM
IDISS_TIME[3:2]
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