DRV2605L Datasheet, PDF (10/69 Pages) Texas Instruments – DRV2605L 2 to 5.2 V Haptic Driver for LRA and ERM With Effect Library and Smart-Loop Architecture

DRV2605L
SLOS854C – MAY 2014 – REVISED SEPTEMBER 2014
8 Detailed Description
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8.1 Overview
The DRV2605L device is a low-voltage haptic driver that relies on the back-EMF produced by an actuator to
provide a closed-loop system that offers extremely flexible control of LRA and ERM actuators over a shared I²C-
compatible bus or PWM input signal. This schema helps improve actuator performance in terms of acceleration
consistency, start time, and brake time.
The improved smart-loop architecture inside the DRV2605L device provides effortless auto-resonant drive for
LRA, as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. These features
create a simplified input waveform paradigm as well as reliable motor control and consistent motor performance.
The DRV2605L device also features automatic transition to open-loop operation in the event that an LRA
actuator is not generating a valid back-EMF voltage and automatic synchronization with the LRA when it is
generating a valid back-EMF voltage. The DRV2605L device also allows for open-loop driving by using internally-
generated PWM. Additionally, the audio-to-vibe mode automatically converts an audio input signal to meaningful
haptic effects.
The DRV2605L device offers a licensed version of TouchSense 2200 software from Immersion which eliminates
the need to design haptic waveforms because the software includes over 100 licensed effects (6 ERM libraries
and 1 LRA library) and audio-to-vibe features. These waveforms can be instantly played back through an I²C or
can be triggered through a hardware trigger pin. Additionally, the real-time playback mode allows the host
processor to bypass the library playback engine and play waveforms directly from the host through the I²C.
The DRV2605L device features a trinary-modulated output stage that provides more efficiency than linear-based
output drivers.
8.2 Functional Block Diagram
V_DD
Supply
correction
ROM
Gate
drive
OUT+
SDA
SCL
EN
IN/TRIG
REG
I²C I/F
REG
Control and
playback
engine
Back-EMF
detection
Gate
drive
LRA
M _or
ERM
OUT±
GND
10
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