DRV2605L Datasheet, PDF (23/69 Pages) Texas Instruments – DRV2605L 2 to 5.2 V Haptic Driver for LRA and ERM With Effect Library and Smart-Loop Architecture

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DRV2605L
SLOS854C – MAY 2014 – REVISED SEPTEMBER 2014
Programming (continued)
8.5.2.2 Overdrive Voltage-Clamp Programming
During closed-loop operation, the actuator feedback allows the output voltage go above the rated voltage during
the automatic overdrive and automatic braking periods. The OD_CLAMP[7:0] bit (in Register 0x17) sets a clamp
so that the automatic overdrive is bounded. The OD_CLAMP[7:0] bit also serves as the full-scale reference
voltage for open-loop operation. The OD_CLAMP[7:0] bit always represents the maximum peak voltage that is
allowed, regardless of the mode.
NOTE
If the supply voltage (V_DD) is less than the overdrive clamp voltage, the output driver is
unable to reach the clamp voltage value because the output voltage cannot exceed the
supply voltage. If the rated voltage exceeds the overdrive clamp voltage, the overdrive
clamp voltage has priority over the rated voltage.
In ERM mode, use Equation 8 to calculate the allowed maximum voltage. In LRA mode, use Equation 9 to
calculate the maximum peak voltage.
V_{(ERM _ clamp)} =
 î ^± î 2'B&/$03>@ î W_{(DRIVE_TIME)} ±  î ^± 
t_{(DRIVE_TIME)}  t_{(IDISS_TIME)}  t_{(BLANKING_TIME)}
(8)
V_{(LRA_clamp)}= 21.22 × 10^± × OD _ CLAMP[7:0]
(9)
8.5.3 I²C Interface
8.5.3.1 General I²C Operation
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with
the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving
device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition
on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the
data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the
SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur
within the low time of the clock period. Figure 20 shows a typical sequence. The master device generates the 7-
bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device
then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge
clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte
of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All
compatible devices share the same signals through a bidirectional bus using a wired-AND connection.
The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word
transfers, the master generates a stop condition to release the bus. Figure 20 shows a generic data-transfer
sequence.
Use external pullup resistors for the SDA and SCL signals to set the logic-high level for the bus. Pullup resistors
with values between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed
the DRV2605L supply voltage, V_DD.
NOTE
The DRV2605L slave address is 0x5A (7-bit), or 1011010 in binary.
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