TMS320DM8148 Datasheet, PDF (306/343 Pages) Texas Instruments – TMS320DM814x DaVinci™ Digital Media Processors

TMS320DM8148, TMS320DM8147
SPRS647 – MARCH 2011
www.ti.com
1
MCB_CLK
2
3
4
MCB_FS
MCB_DX
4
5
5
MCB_DX7
5
MCB_DX6
MCB_DX0
MCB_DR
7
6
MCB_DR7
MCB_DR6
MCB_DR0
A. The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive
output data and capture input data.
B. MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either
MCBSP_FSX
or
MCBSP_FSR.
McBSP in 6-pin mode: DX and DR as data pins; CLKX, CLKR, FSX and FSR as control pins.
McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are
internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.
C. The polarity of McBSP frame synchronization is software configurable.
D. The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and
MCBSP_DR data is sampled is software configurable.
E. Timing diagrams are for data delay set to 1.
F. For further details about the registers used to configure McBSP, see the TMS320DM814x DMSoC Multichannel
Buffered Serial Port (McBSP) User's Guide (TBD).
Figure 8-83. McBSP Master Mode Timing
Table 8-76. Timing Requirements for McBSP - Slave Mode⁽¹⁾
(see Figure 8-84)
NO.
1 t_c(CLK)
2 t_w(CLKL)
3 t_w(CLKH)
4 t_{su(FSV-CLKAE)}
5 t_h(CLKAE-FSV)
7 t_{su(DRV-CLKAE)}
8 t_h(CLKAE-DRV)
Cycle time, MCB_CLK period⁽²⁾
Pulse duration, MCB_CLK low⁽²⁾
Pulse duration, MCB_CLK high⁽²⁾
Setup time, MCB_FS valid before MCB_CLK active edge⁽²⁾⁽⁴⁾
Hold time, MCB_FS valid after MCB_CLK active edge⁽²⁾⁽⁴⁾
Setup time, MCB_DR valid before MCB_CLK active edge⁽²⁾
Hold time, MCB_DR valid after MCB_CLK active edge⁽²⁾
OPP100
MIN
20.83
0.5*P - 1⁽³⁾
0.5*P - 1⁽³⁾
3.8
0
3.8
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.
(3) P = MCB_CLKX/MCB_CLKR output CLK period, in ns; use whichever value is greater. This parameter applies to the maximum McBSP
frequency. Operate serial clocks (CLKX/R) in the reasonable range of 40/60 duty cycle.
(4) MCB_FS corresponds to either MCB_FSX or MCB_FSR.
Table 8-77. Switching Characteristics Over Recommended Operating Conditions for McBSP - Slave
Mode ⁽¹⁾
(see Figure 8-84)
NO.
PARAMETER
OPP100
UNIT
MIN
MAX
6 t_{d(CLKXAE-DXV)}
Delay time, input MCB_CLKx active edge to output MCB_DX valid
0.5
12.5 ns
(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture
input data.
306 Peripheral Information and Timings
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