TMS320DM8148 Datasheet, PDF (255/343 Pages) Texas Instruments – TMS320DM814x DaVinci™ Digital Media Processors

TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647 – MARCH 2011
8.11 Inter-Integrated Circuit (I2C)
The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• Seven- and ten-bit device addressing modes
• Multimaster transmitter/slave receiver mode
• Multimaster receiver/slave transmitter mode
• Combined master transmit/receive and receive/transmit modes
• Two DMA channels, one interrupt line
• Built-in FIFO (32 byte) for buffered read or write.
For more detailed information on the I2C peripheral, see the TMS320DM814x DMSoC Inter-Integrated
Circuit (I2C) User's Guide (TBD).
8.11.1 I2C Peripheral Register Descriptions
I2C0 HEX ADDRESS
0x4802 8000
0x4802 8004
0x4802 8010
0x4802 8020
0x4802 8024
0x4802 8028
0x4802 802C
0x4802 8030
0x4802 8034
0x4802 8038
0x4802 803C
0x4802 8040
0x4802 8044
0x4802 8048
0x4802 804C
0x4802 8090
0x4802 8094
0x4802 8098
0x4802 809C
0x4802 80A4
0x4802 80A8
0x4802 80AC
0x4802 80B0
0x4802 80B4
0x4802 80B8
0x4802 80BC
Table 8-39. I2C Registers
I2C1 HEX ADDRESS
0x4802 A000
0x4802 A004
0x4802 A010
0x4802 A020
0x4802 A024
0x4802 A028
0x4802 A02C
0x4802 A030
0x4802 A034
0x4802 A038
0x4802 A03C
0x4802 A040
0x4802 A044
0x4802 A048
0x4802 A04C
0x4802 A090
0x4802 A094
0x4802 A098
0x4802 A09C
0x4802 A0A4
0x4802 A0A8
0x4802 A0AC
0x4802 A0B0
0x4802 A0B4
0x4802 A0B8
0x4802 A0BC
ACRONYM
I2C_REVNB_LO
I2C_REVNB_HI
I2C_SYSC
I2C_EOI
I2C_IRQSTATUS_RAW
I2C_IRQSTATUS
I2C_IRQENABLE_SET
I2C_IRQENABLE_CLR
I2C_WE
I2C_DMARXENABLE_SET
I2C_DMATXENABLE_SET
I2C_DMARXENABLE_CLR
I2C_DMATXENABLE_CLR
I2C_DMARXWAKE_EN
I2C_DMATXWAKE_EN
I2C_SYSS
I2C_BUF
I2C_CNT
I2C_DATA
I2C_CON
I2C_OA
I2C_SA
I2C_PSC
I2C_SCLL
I2C_SCLH
I2C_SYSTEST
REGISTER NAME
Module Revision (LOW BYTES)
Module Revision (HIGH BYTES)
System configuration
I2C End of Interrupt
I2C Status Raw
I2C Status
I2C Interrupt Enable Set
I2C Interrupt Enable Clear
I2C Wakeup Enable
Receive DMA Enable Set
Transmit DMA Enable Set
Receive DMA Enable Clear
Transmit DMA Enable Clear
Receive DMA Wakeup
Transmit DMA Wakeup
System Status
Buffer Configuration
Data Counter
Data Access
I2C Configuration
I2C Own Address
I2C Slave Address
I2C Clock Prescaler
I2C SCL Low Time
I2C SCL High Time
System Test
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Timings 255
Submit Documentation Feedback
Product Folder Link(s): TMS320DM8148 TMS320DM8147