TMS320DM8148 Datasheet, PDF (226/343 Pages) Texas Instruments – TMS320DM814x DaVinci™ Digital Media Processors

TMS320DM8148, TMS320DM8147
SPRS647 – MARCH 2011
www.ti.com
8.7 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register controls the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt generation
modes. The GPIO peripheral provides generic connections to external devices.
The device contains four GPIO modules and each GPIO module is made up of 32 identical channels.
The device GPIO peripheral supports the following:
• Up to 128 1.8-V/3.3-V GPIO pins, GP0[0:31], GP1[0:31], GP2[0:31], and GP3[0:31] (the exact number
available varies as a function of the device configuration). Each channel can be configured to be used
in the following applications:
– Data input/output
– Keyboard interface with a de-bouncing cell
– Synchronous interrupt generation (in active mode) upon the detection of external events (signal
transition(s) and/or signal level(s)).
• Synchronous interrupt requests from each channel are processed by four identical interrupt generation
sub-modules to be used independently by the ARM, DSP, or Media Controller. Interrupts can be
triggered by rising and/or falling edge, specified for each interrupt-capable GPIO signal.
• Shared registers can be accessed through "Set & Clear" protocol. Software writes 1 to corresponding
bit position(s) to set or to clear GPIO signal(s). This allows multiple software processes to toggle GPIO
output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts,
to prevent context switching to another process during GPIO programming).
• Separate input/output registers.
• Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic to be implemented.
For more detailed information on GPIOs, see the TMS320DM814x General-Purpose Input/Output (GPIO)
User's Guide (TBD).
8.7.1 GPIO Peripheral Register Descriptions TBD
GPIO0 HEX ADDRESS
0x4803 2000
0x4803 2010
0x4803 2020
0x4803 2024
0x4803 2028
0x4803 202C
0x4803 2030
0x4803 2034
0x4803 2038
0x4803 203C
0x4803 2040
0x4803 2044
0x4803 2048
0x4803 2114
0x4803 2130
Table 8-24. GPIO Registers
GPIO1 HEX ADDRESS
0x4804 C000
0x4804 C010
0x4804 C020
0x4804 C024
0x4804 C028
0x4804 C02C
0x4804 C030
0x4804 C034
0x4804 C038
0x4804 C03C
0x4804 C040
0x4804 C044
0x4804 C048
0x4804 C114
0x4804 C130
ACRONYM
GPIO_REVISION
GPIO_SYSCONFIG
GPIO_EOI
GPIO_IRQSTATUS_RAW_0
GPIO_IRQSTATUS_RAW_1
GPIO_IRQSTATUS_0
GPIO_IRQSTATUS_1
GPIO_IRQSTATUS_SET_0
GPIO_IRQSTATUS_SET_1
GPIO_IRQSTATUS_CLR_0
GPIO_IRQSTATUS_CLR_1
GPIO_IRQWAKEN_0
GPIO_IRQWAKEN_1
GPIO_SYSSTATUS
GPIO_CTRL
REGISTER NAME
GPIO Revision
System Configuration
End of Interrupt
Status Raw for Interrupt 1
Status Raw for Interrupt 2
Status for Interrupt 1
Status for Interrupt 2
Enable Set for Interrupt 1
Enable Set for Interrupt 2
Enable Clear for Interrupt 1
Enable Clear for Interrupt 2
Wakeup Enable for Interrupt 1
Wakeup Enable for Interrupt 2
System Status
Module Control
226 Peripheral Information and Timings
Copyright © 2011, Texas Instruments Incorporated
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