TMS320DM8148 Datasheet, PDF (158/343 Pages) Texas Instruments – TMS320DM814x DaVinci™ Digital Media Processors

TMS320DM8148, TMS320DM8147
SPRS647 – MARCH 2011
www.ti.com
5 System Interconnect
The device’s various processors, subsystems, and peripherals are interconnected through a switch fabric
architecture. The switch fabric is composed of an L3 and L4 interconnect, a switched central resource
(SCR), and multiple bridges (for an overview, see Figure 5-1). Not all Initiators in the switch fabric are
connected to all Target peripherals. The supported initiator and target connections are designated by a "X"
in Table 5-1, Target/Initiator Connectivity.
For more detailed information on the device System Interconnect Architecture, see the TBD System
User's Guide (Literature Number: TBD).
DSP MDMA
EDMATC RD 0/1
EDMATC WR 0/1
ARM Cortex
A8
L3F
Initiators
EDMATC RD 2/3
EDMATC WR 2/3
HDVICP
HDVPSS (2 I/F)
ISS
SGX530
128b
64b
128b
1 I/F
9 I/F
DSP/
EDMA
MMU
L3F
Initiators
PCIe
MEDIACTL
128b
128b
64b
1 I/F
4 I/F
2 I/F
L3F
Initiators
DSP CFG
EMAC SW
SATA
DAP
32b
7 I/F
L3S Initiators
USB2.0 (2 I/F)
32b
4 I/F
L3F/L3Mid
Interconnect
200 MHz (Note 2)
L3S Interconnect
100 MHz (Note 2)
2 I/F
128b _128b
2 I/F
128b
5 I/F
64b
11 I/F
32b
2 I/F
32b
8 I/F
32b
2 I/F
32b
DMM
L3F
Targets
DDR0
DDR1
DSP SDMA
HDVICP SL2
L3F
Targets
PCIe
MEDIACTL
SGX530
OCMC SRAM
L3F
Targets
ISS
MMCSD 2
HDVICP CFG
EDMATC 0/1/2/3
EDMACC
DEBUGSS
L4F
Interconnect
200 MHz
(Note 2)
11 I/F
L3S Targets
MCASP 0/1 / 2 Data
MCBSP
GPMC
HDMI
USB
L4S
Interconnect
100 MHz
(Note2)
58 I/F
32b
32b
L4F Targets
EMAC SW
SATA
MCASP #3/4/5 CFG
MCASP #3/4/5 DATA
Note 1 : TPTC 0/1 RD/WR transactions can optionally be routed through System MMU using chip control module
Note 2 : The frequencies specified are for 100% OPP
L4S Targets
MMU
UART 0/1/2/3/4/5
I2C 0/1/2/3
DMTimer 0/1/2/3/4/5/6/7/8
SPI 0/1/2/3
GPIO 0/1/2/3
MCASP 0/1/2 CFG
MMCSD 0 /1
ELM
RTC
WDT 0/1
Mailbox
Spinlock
HDVPSS
HDMIPHY
PLLSS
Control Module
PRCM
SmartReflex 0/1/2/3
DCAN 0/1
OCPWP
RTC
SYNCTIMER32K
158 System Interconnect
Figure 5-1. System Interconnect
Copyright © 2011, Texas Instruments Incorporated
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