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| TMS320DM8148 Datasheet, PDF (211/343 Pages) Texas Instruments – TMS320DM814x DaVinci™ Digital Media Processors | |||
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TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647 â MARCH 2011
8.5.3.1 JTAG ID (JTAGID) Register Description
Table 8-5. JTAG ID Register(1)
HEX ADDRESS
0x4814 0600
ACRONYM
JTAGID
REGISTER NAME
JTAG Identification Register(2)
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
(2) Read-only. Provides the device 32-bit JTAG ID.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this
device, the JTAG ID register resides at address location 0x4814 0600. The register hex value for the
device is: 0x0B8F 202F. For the actual register bit names and their associated bit field descriptions, see
Figure 8-5 and Table 8-6.
31
28 27
VARIANT
(4-bit)
PART NUMBER (16-bit)
R-xxxx
R-1011 1000 1111 0010
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
12 11
MANUFACTURER (11-bit)
R-0000 0010 111
10
LSB
R-1
Figure 8-5. JTAG ID Register Description - Device Register Value: 0x0B8F 202F
Bit
31:28
27:12
11:1
0
Table 8-6. JTAG ID Register Selection Bit Descriptions
Field
Description
VARIANT
Variant (4-bit) value. Device value: xxxx. This value reflects the device silicon revision [For example, 0x0
(0000) for initial silicon (1.0)]. For more detailed information on the current device silicon revision(s), see
TBD Silicon Errata (Literature Number: SPRZTBD).
PART NUMBER Part Number (16-bit) value. Device value: 0xB8F2 (1011 1000 1111 0010)
MANUFACTURER Manufacturer (11-bit) value. Device value: 0x017 (0000 0010 111)
LSB
LSB. This bit is read as a ""1 for this device.
8.5.3.2 JTAG Electrical Data/Timing
(see Figure 8-6)
NO.
1 tc(TCK)
1a tw(TCKH)
1b tw(TCKL)
3 tsu(TDI-TCK)
3 tsu(TMS-TCK)
4
th(TCK-TDI)
th(TCK-TMS)
Table 8-7. Timing Requirements for IEEE 1149.1 JTAG
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high (20% of (tc * 0.5))
Input setup time, TMS valid to TCK high (20% of (tc * 0.5))
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
OPP100
MIN
51.15
20.46
20.46
5.115
5.115
10
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 8-8. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
(see Figure 8-6)
NO.
2 td(TCKL-TDOV)
PARAMETER
Delay time, TCK low to TDO valid
OPP100
MIN
MAX
0 23.575(1)
UNIT
ns
(1) (0.5 * tc) - 2
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Timings 211
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Product Folder Link(s): TMS320DM8148 TMS320DM8147
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