TM4C129LNCZAD Datasheet, PDF (293/2140 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129LNCZAD Microcontroller
Bit/Field
9:0
Name
DSSYSDIV
Type
RW
Reset
0x0
Description
Deep Sleep Clock Divisor
This field specifies the system clock divisor value during deep sleep
mode. The clock source selected by DSOSCSRC is divided by DSSYSDIV
+ 1:
f_SYSCLK=f_OSCCLK/(DSSYSDIV + 1)
Note:
Values 0x0 and 0x1 should not be used. If Deep-Sleep clock
divide by 1 or divide by 2 is desired, the OSYSDIV bit field of
the RSCLKCFG register must be configured for the desired
Deep-Sleep divider before entering Deep-Sleep. In this case,
the Q post-divider bit field in the PLLFREQ1 register may
need to be adjusted to keep the system clock frequency within
the maximum clock frequency before entering Deep-Sleep.
June 18, 2014
293
Texas Instruments-Production Data