TM4C129LNCZAD Datasheet, PDF (156/2140 Pages) Texas Instruments – Tiva Microcontroller

Cortex-M4 Peripherals
Control (CPAC) register. The below example code sequence enables the FPU in both privileged
and user modes.
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB
3.2 Register Map
Table 3-8 on page 156 lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers.
The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-8. Peripherals Register Map
Offset Name
Type
Reset
Description
System Timer (SysTick) Registers
0x010 STCTRL
RW
0x0000.0000
0x014 STRELOAD
RW
-
0x018 STCURRENT
RWC
-
Nested Vectored Interrupt Controller (NVIC) Registers
0x100 EN0
RW
0x0000.0000
0x104 EN1
RW
0x0000.0000
0x108 EN2
RW
0x0000.0000
0x10C EN3
RW
0x0000.0000
0x180 DIS0
RW
0x0000.0000
0x184 DIS1
RW
0x0000.0000
0x188 DIS2
RW
0x0000.0000
0x18C DIS3
RW
0x0000.0000
0x200 PEND0
RW
0x0000.0000
0x204 PEND1
RW
0x0000.0000
0x208 PEND2
RW
0x0000.0000
0x20C PEND3
RW
0x0000.0000
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
Interrupt 0-31 Set Enable
Interrupt 32-63 Set Enable
Interrupt 64-95 Set Enable
Interrupt 96-113 Set Enable
Interrupt 0-31 Clear Enable
Interrupt 32-63 Clear Enable
Interrupt 64-95 Clear Enable
Interrupt 96-113 Clear Enable
Interrupt 0-31 Set Pending
Interrupt 32-63 Set Pending
Interrupt 64-95 Set Pending
Interrupt 96-113 Set Pending
See
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June 18, 2014
Texas Instruments-Production Data