TM4C129LNCZAD Datasheet, PDF (1575/2140 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129LNCZAD Microcontroller
3. The DMA decodes the receive data buffer address from the acquired descriptors.
4. Incoming frames are processed and placed in the acquired descriptor's data buffers.
5. When the buffer is full or the frame transfer is complete, the RX DMA engine fetches the next
descriptor.
6. If the current frame transfer is complete, the DMA proceeds to Step 7. If the DMA does not own
the next fetched descriptor and the frame transfer is not complete (EOF is not yet transferred),
the DMA sets the Descriptor Error (DE) bit in RDES0 (unless flushing is disabled through the
DFF bit in the EMACDMAOPMODE register). The DMA closes the current descriptor (clears
the OWN bit) and marks it as intermediate by clearing the Last Segment (LS) bit in the RDES0
value. If flushing is not disabled, then the DMA would mark it as the last descriptor. In either
case, the DMA proceeds to Step 8. If the DMA does own the next descriptor but the current
frame transfer is not complete, the DMA closes the current descriptor as intermediate and reverts
to Step 4.
7. If IEEE 1588 timestamping is enabled, the DMA writes the timestamp to the current descriptor's
RDES6 and RDES7. It then takes the receive frame's status and writes the status word to the
current descriptor's RDES0, with the OWN bit cleared and the Last Segment (LS) bit set. If the
host stopped the RX DMA by clearing the SR bit of the EMACDMAOPMODE register, DMA
goes to the STOP state, otherwise the RX DMA proceeds to Step 8.
8. The RX DMA engine checks the last descriptor's OWN bit. If the CPU owns the descriptor (OWN
bit is 0), the RU bit of the EMACDMARIS register is set and the DMA RX engine enters the
SUSPEND state. If the DMA owns the descriptor, the engine returns to Step 4 and awaits the
next frame.
9. Before the RX DMA engine enters the SUSPEND state, partial frames are flushed from the RX
FIFO. Flushing can be controlled through the DFF bit of the EMACDMAOPMODE register.
10. The RX DMA enters the STOP state if the CPU has cleared the SR bit of the
EMACDMAOPMODE register. Otherwise, it exits the SUSPEND state when a Receive Poll
Demand is given or the start of the next frame is available from the RX FIFO. The DMA engine
proceeds to Step 2 and re-fetches the next descriptor.
The DMA does not acknowledge accepting status from the TX/RX Controller until it has completed
the timestamp write-back and is ready to perform status write-back to the descriptor.
If software has enabled timestamping through the Ethernet MAC Timestamp Control
(EMACTIMSTCTRL) register, offset 0x700, when a valid timestamp is not available for the frame
(for example, because the receive FIFO was full before the timestamp could be written to it), the
DMA writes all-ones to RDES6 and RDES7. Otherwise if timestamping is not enabled, RDES6 and
RDES7 remain unchanged.
Figure 23-7 on page 1576 shows the flow of a RX DMA Operation.
June 18, 2014
Texas Instruments-Production Data
1575