TM4C129LNCZAD Datasheet, PDF (1226/2140 Pages) Texas Instruments – Tiva Microcontroller

Analog-to-Digital Converter (ADC)
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note:
For a 1 to 2 Msps rate, as the system clock frequency approaches the ADC clock frequency,
it is recommended that the application use the µDMA to store conversion data from the
FIFO to memory before processing rather than an interrupt-driven single data read. Using
the µDMA to store multiple samples before interrupting the processor amortizes interrupt
overhead across multiple transfers and prevents loss of sample data.
Note:
Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
DMAMASK3 DMAMASK2 DMAMASK1 DMAMASK0
RO
RW
RW
RW
RW
RO
0
0
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
DCONSS3 DCONSS2 DCONSS1 DCONSS0
RO
RW
RW
RW
RW
0
0
0
0
0
4
3
2
1
0
MASK3 MASK2 MASK1 MASK0
RO
RW
RW
RW
RW
0
0
0
0
0
Bit/Field
31:20
19
Name
reserved
DCONSS3
Type
RO
RW
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator Interrupt on SS3
Value Description
0 The status of the digital comparators does not affect the SS3
interrupt status.
1 The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
18
DCONSS2
RW
0
Digital Comparator Interrupt on SS2
Value Description
0 The status of the digital comparators does not affect the SS2
interrupt status.
1 The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
1226
Texas Instruments-Production Data
June 18, 2014