TM4C129LNCZAD Datasheet, PDF (128/2140 Pages) Texas Instruments – Tiva Microcontroller

The Cortex-M4F Processor
2.5.3
2.5.4
Table 2-9. Interrupts (continued)
Vector Number
125
126
127
129
Interrupt Number (Bit
in Interrupt Registers)
109
110
111
113
Vector Address or
Offset
0x0000.01F4
0x0000.01F8
0x0000.01FC
-
Description
I²C 8
I²C 9
GPIO T
Reserved
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 124. Figure 2-6 on page 129 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
128
June 18, 2014
Texas Instruments-Production Data