TM4C129LNCZAD Datasheet, PDF (1791/2140 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129LNCZAD Microcontroller
Note:
Port pins PL6 and PL7 operate as Fast GPIO pads, but have 4-mA drive capability only.
GPIO register controls for drive strength, slew rate and open drain have no effect on these
pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R,
GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 765 and “Recommended GPIO Operating
Characteristics” on page 2053 for more information.
Table 24-1. USB Signals (212BGA)
Pin Name
USB0CLK
USB0D0
USB0D1
USB0D2
USB0D3
USB0D4
USB0D5
USB0D6
USB0D7
USB0DIR
Pin Number Pin Mux / Pin
Assignment
B17
PB3 (14)
G16
PL0 (14)
H19
PL1 (14)
G18
PL2 (14)
J18
PL3 (14)
H18
PL4 (14)
G19
PL5 (14)
B12
PP5 (14)
D8
PP4 (14)
C12
PP3 (14)
Pin Type
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
USB0DM
B18
PL7
I/O
USB0DP
C18
PL6
I/O
USB0EPEN
USB0ID
V5
PA6 (5)
O
R7
PA7 (11)
B3
PD6 (5)
A16
PB0
I
USB0NXT
USB0PFLT
USB0STP
USB0VBUS
B13
PP2 (14)
O
R7
PA7 (5)
I
B2
PD7 (5)
A17
PB2 (14)
O
B16
PB1
I/O
Buffer Type Description
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Analog
Analog
TTL
60-MHz clock to the external PHY.
USB data 0.
USB data 1.
USB data 2.
USB data 3.
USB data 4.
USB data 5.
USB data 6.
USB data 7.
Indicates that the external PHY is able to accept
data from the USB controller.
Bidirectional differential data pin (D- per USB
specification) for USB0.
Bidirectional differential data pin (D+ per USB
specification) for USB0.
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
Analog
TTL
TTL
TTL
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
Asserted by the external PHY to throttle all data
types.
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
Asserted by the USB controller to signal the end of
a USB transmit packet or register write operation.
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
24.3
Register Map
Table 24-2 on page 1792 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 407). There must be a delay of 3 system clocks after the USB module clock
is enabled before any USB module registers are accessed.
June 18, 2014
Texas Instruments-Production Data
1791