TM4C129LNCZAD Datasheet, PDF (1735/2140 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129LNCZAD Microcontroller
Register 72: Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR), address
0x000
This register describes the basic mode controls available to the EPHY. The reset state of the ANEN
bit is controlled by the EMACPC register.
Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR)
Base n/a
Address 0x000
Type RW, reset 0x3100
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MIIRESET MIILOOPBK SPEED ANEN PWRDWN ISOLATE RESTARTAN DUPLEXM COLLTST
reserved
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
Bit/Field
15
Name
MIIRESET
Type
RW
Reset
0
Description
MII Register reset
Writing a 1 to this bit resets the contents of the MII-related registers,
EPHYBMCR (0x000) EPHYANA (0x004) and EPHYANNPTR (0x007)
registers . When the reset operation is done, this bit is cleared to 0
automatically.
Value Description
0 Normal operation.
1 Initiate MII Reset / Reset in Process.
14
MIILOOPBK
RW
0
MII Loopback
When MII loopback mode is activated, the transmitter data presented
on MII TXD is looped back to MII RXD internally.
Value Description
0 Normal operation.
1 MII Loopback enabled.
13
SPEED
RW
1
Speed Select
When auto-negotiation is disabled writing to this bit allows the port speed
to be selected.
Value Description
0 10Mbs
1 100Mbs
12
ANEN
RW
1
Auto-Negotiate Enable
Value Description
0 Auto-Negotiation Disabled – the SPEED bit and the DUPLEXM
bit determine the port speed and duplex mode.
1 Auto-Negotiation Enabled – the SPEED bit and the DUPLEXM bit
of this register are ignored when this bit is set.
June 18, 2014
Texas Instruments-Production Data
1735